Conventional processor systems can implement an instruction pipeline to increase throughput of processor instructions (e.g., load instructions and store instructions). For example, an instruction pipeline can be divided into multiple stages (e.g., fetch instruction, decode instruction, execute instruction, write-back instruction, etc.) to allow processing of multiple processor instructions in parallel. In certain implementations, a processor can implement out-of-order execution to execute processor instructions based on availability (e.g., availability of processor instructions) rather than an original program order for the processor instructions. For example, each processor instruction (e.g., load instruction and/or store instruction) can be stored in a data structure when decoding operations associated with processor instructions. The processor instructions (e.g., load instructions and/or stores instructions) can then be permitted to execute out-of-order. As such, a processor can avoid being in an idle state while data is retrieved for a next processor instruction (e.g., a processor can process a next processor instruction as soon as data operands associated with the next processor instruction are available).
However, out-of-order execution can lead to memory order violations (e.g., reordering issues), incorrect data, etc. For example, out-of-order execution can lead to an instruction pipeline hazard (e.g., a write after read (WAR) hazard, a write after write (WAW) hazard, etc.). Conventionally, if it is determined that a memory order violation (e.g., an instruction pipeline hazard) has occurred, the violating processor instruction (e.g., load instruction or store instruction) and each subsequent processor instruction are re-executed (e.g., the data structure employed for out-of-order execution is erased and/or reformatted). Therefore, accuracy and/or efficiency of conventional techniques for executing processor instructions (e.g., load instructions and/or store instructions) out-of-order can be improved.